參數(shù)資料
型號(hào)： 93V850DGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： 0.240 INCH, MO-153, TSSOP-48
文件頁(yè)數(shù)： 6/10頁(yè)
文件大?。?/td> 194K
代理商： 93V850DGT
5
ICS93V850
Preliminary Product Preview
0423H—07/03/03
Notes:
1.
Refers to transition on noninverting output.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Operating clock frequency
freqop
66
170
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
from VDD = 3.3V to 1%
target freq.
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
66MHz
120
ps
100/125/133/167MHz
75
ps
66MHz
110
ps
100/125/133/167MHz
65
ps
Phase error
t(phase error)
-150
150
ps
Output to Output Skew
Tskew
100
ps
Pulse skew
Tskewp
100
ps
Half Period Jitter
Tjitter Hp
66/100/133/166MHz
-75
75
ps
Typ: Propagation Delay
Time
Bypass Mode CLK to
any output
4ns
Slew Rate
tSLEW
Load = 120
/14pF
1
1.8
2
V/ns
Jitter; Absoulte Jitter
Tjabs
Cycle to Cycle Jitter
1
Tcyc-Tcyc
Recommended Operating Condition
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD, AVDD
2.3
2.5
2.7
V
VDDI2C
2.3
3.6
V
VIL
-0.3
VDD-0.4
V
VIH
0.4
VDD+0.3
V
DC - CLK_INT, FB_INT
0.36
VDDQ +0.6
V
AC - CLK_INT, FB_INT
0.5
VDDQ +0.6
V
Input differential-pair
crossing voltage
VIC
0.45x(VIH-VIL)
0.55x(VIH-VIL)V
Output differential-pair
crossing voltage
VOC
V
1 Differential inputs signal voltages specifies the differential voltage [VTR - VCP] required for switching,
where VT is the true input level and VCP is the complementary input level.
Input differential-pair
voltage swing
1
VID
Analog/core supply
voltage
Input voltage level
相關(guān)PDF資料
PDF描述
93V855AGLFT 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
93V855AGLF 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
93V855AG 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
93V855AGI 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
93V857BG-025LF-T 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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