參數(shù)資料
型號(hào): 93LC56CST
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 2K Microwire Compatible Serial EEPROM
中文描述: 2K微絲兼容串行EEPROM
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 222K
代理商: 93LC56CST
93LC46/56/66
DS11168L-page 6
1997 Microchip Technology Inc.
3.4
ERASE
The ERASE instruction forces all data bits of the spec-
ied address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specied address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word (Typical).
3.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
FIGURE 3-2:
ERASE TIMING
FIGURE 3-3:
ERAL TIMING
CLK
CS
TCSL
1
DI
An
BUSY
A0
READY
TWC
DO
1
CHECK STATUS
STANDBY
TCZ
TRI-STATE
TSV
TRI-STATE
An-1
An-2
CLK
CS
TCSL
0
DI
0
BUSY
0
READY
T EC
DO
1
CHECK STATUS
STANDBY
T CZ
TRI-STATE
TSV
TRI-STATE
Guarantee at Vcc = +4.5V to +6.0V.
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