參數(shù)資料
型號: 93LC56CST
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 2K Microwire Compatible Serial EEPROM
中文描述: 2K微絲兼容串行EEPROM
文件頁數(shù): 11/12頁
文件大?。?/td> 222K
代理商: 93LC56CST
93LC46/56/66
DS11168L-page 8
1997 Microchip Technology Inc.
3.8
WRITE
The WRITE instruction is followed by 8 bits (or by 16
bits) of data which are written into the specied
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specied address has been written with the data
specied and the device is ready for another instruc-
tion.
The WRITE cycle takes 4 ms per word (Typical).
3.9
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specied in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The WRAL command does
include an automatic ERAL cycle for the device. There-
fore, the WRAL instruction does not require an ERAL
instruction, but the chip must be in the EWEN status.
The WRAL instruction is guaranteed at VCC = +4.5V to
+6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRAL cycle takes 30 ms maximum (16 ms typical).
FIGURE 3-7:
WRITE TIMING
FIGURE 3-8:
WRAL TIMING
CLK
CS
TCSL
0
1
DI
BUSY
D0
A
1
A0
Dx
READY
TWC
DO
TRI-STATE
n
STANDBY
TRI_STATE
CLK
CS
TCSL
0
1
DI
BUSY
D0
X
0
X
Dx
READY
TWL
DO
0
1
TRI-STATE
STANDBY
Guarantee at Vcc = +4.5V to +6.0V.
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