參數(shù)資料
型號(hào): 93C76T-E/SNVAO
元件分類: PROM
英文描述: 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 102K
代理商: 93C76T-E/SNVAO
1998 Microchip Technology Inc.
DS21132D-page 5
93C76/86
2.0
PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/BUSY status dur-
ing a programming operation. The READY/BUSY sta-
tus can be veried during an Erase/Write operation by
polling the DO pin; DO low indicates that programming
is still in progress, while DO high indicates the device is
ready. The DO will enter the high impedance state on
the falling edge of the CS.
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the rst time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this conguration it is possible
for a “bus conict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undened and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the Data Out pin.
2.3
Erase/Write Enable and Disable
(EWEN, EWDS)
The 93C76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should
follow all programming operations. Execution of a
READ instruction is independent of both the EWEN
and EWDS instructions.
2.4
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
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