參數(shù)資料
型號: 93C76T-E/SNVAO
元件分類: PROM
英文描述: 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁數(shù): 13/13頁
文件大小: 102K
代理商: 93C76T-E/SNVAO
1998 Microchip Technology Inc.
DS21132D-page 9
93C76/86
FIGURE 3-8:
ERAL
Guarantee at VCC = +4.5V to +5.5V.
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
10
01
0
X
...
CS
CLK
DI
DO
TEC
TCZ
HIGH IMPEDANCE
BUSY
READY
STANDBY
4.0
PIN DESCRIPTIONS
4.1
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
4.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specied number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 1-4
through Table 1-7 for more details). CLK and DI then
become don't care inputs waiting for a new start condi-
tion to be detected.
4.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
4.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available when CS is high. It will
be displayed until the next start bit occurs as long as
CS stays high.
4.5
Organization (ORG)
When ORG is connected to VCC, the x16 memory orga-
nization is selected. When ORG is tied to VSS, the x8
memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16
organization when left unconnected.
4.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is
oated or tied to VCC, the device can be programmed.
If the PE pin is tied to VSS, programming will be inhib-
ited. There is an internal pull-up on this device that
enables programming if this pin is left oating.
Note:
CS must go LOW between consecutive
instructions, except when performing a
sequential read (Refer to Section 3.1 for
more detail on sequential reads).
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