
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-24
9
FTGL
R/W
0
Field toggle mode
0 = normal
1 = free toggle (sequence starts with FID = 0)
8:4
reserved
-
3
SF
R/W
0
Swap eld interpretation
0: odd (rst) eld = 0, even (second) eld = 1
1: odd (rst) eld = 1, even (second) eld = 0
2
FZERO
R/W
0
Force FID value to zero
0 = eld identier derived from input stream
1 = force eld identier value to 0
1
REVS
R/W
0
Vertical sync reference edge
0 = falling edge / start of active video
1 = rising edge / end of active video
0
REHS
R/W
0
Horizontal sync reference edge
0 = falling edge / SAV
1 = rising edge / EAV
Offset 0x10 6104
Video Test Pattern Generator Control
31
PAL
R/W
0
Field generation mode
0 = NTSC timing
1 = PAL timing
30
reserved
0
29
VSEL
R/W
0
Vertical timing signal select (will be removed)
0 = generate VREF
1 = generate VS
28
HSEL
R/W
0
Horizontal timing signal select (will be removed)
0 = generate HREF
1 = generate HS
27
SWAP
R/W
0
Alternative test pattern
0 = normal test pattern
1 = test pattern with diagonal patterns, etc.
26
MOVE
R/W
0
Scrolling enable for alternative test pattern
0 = no scrolling
1 = scrolling enabled
25:0
reserved
0
Video Acquisition Window Control Registers
Offset 0x10 6140
Video Acquisition Window Start
31:27
reserved
-
26:16
VID_XWS[10:0]
R/W
0
Horizontal video window start
The pixel co-sited with the reference edge REHS is numbered 0.
15:11
reserved
-
10:0
VID_YWS[10:0]
R/W
0
Vertical video window start
The rst line indicated by the reference edge REVS is numbered 0.
Offset 0x10 6144
Video Acquisition Window End
31:27
reserved
-
Table 10: Video Input Processor (VIP) 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description