
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-23
Video Informations Registers
Offset 0x10 6040
VIP Line Threshold
31:11
reserved
10:0
LCTHR[10:0]
R/W
0
Video line count threshold
Line threshold status bit is set if video line count (SVLC) reaches
this value
Note: It is possible to have multiple interrupts per eld at different
line counts, by re-programming the threshold value in this register
from the ISR.
Input Format Control Registers
Offset 0x10 6100
Video Input Format
31:30
VSRA[1:0]
R/W
0
Video stream realignment
00 = normal
01 = ignore 1st sample after HREF
1x = reserved
29:26
reserved
-
25
SYNCHD
R/W
0
HD sync select
0 = embedded sync
1 = explicit sync
24
DUAL_STREAM
R/W
0
Dual video data stream enable
0 = single video data stream mode
1 = dual video data stream mode
23:21
reserved
-
20
NHDAUX
R/W
0
header detect during AUX window
0 = D1 header detection enabled inside AUX window
1 = D1 header detection disabled inside AUX window
19
NPAR
R/W
0
Parity check disable
0 = parity check enabled for D1 header detection
1 = parity check disabled for D1 header detection
18:16
reserved
-
15:14
VSEL[1:0]
R/W
0
Video source select
00 = reserved
01 = video port, encoded sync (D1-Mode)
10 = video port, external sync (VMI-Mode)
11 = reserved
13
TWOS
R/W
0
UV data type
0 = offset binary
1 = two’s complement
12
TPG
R/W
0
Test pattern generator
0 = video stream selected by VSEL
1 = internal test pattern generator
11:10
reserved
-
10
FREF
R/W
0
Field toggle reference mode
0 = normal, use VREF
1 = toggling Field bit is used as vertical reference
Table 10: Video Input Processor (VIP) 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description