
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
16-5
3.
Operation
3.1 Clock Programming
Figure 2 illustrates the clocking capabilities of the Audio Input unit. Driving the system
is a square wave Direct Digital Synthesizer (DDS). The DDS can be programmed to
emit frequencies from approximately 1 Hz to 40 MHz with a resolution of better than
0.3 Hz. The DDS and its control registers reside in the Clocks module outside the
Audio in Unit.
The output of the DDS is always sent on the OSCLK output pin. This output is
intended to be used as the 256 fs or 384 fs system clock source for oversampling A/D
converters.
Software may change the DDS frequency setting dynamically, so as to adjust the
input sampling rate to track an application dependent master reference. Using the
DDS function, a high quality, low-jitter OSCLK is generated.
3.1.1
Clock System Operation
SCK and WS can be congured as input or output, as determined by the
SER_MASTER control eld. As an output, SCK is a divided form of the OSCLK
output frequency. The SCKDIV register value is used to divide down the OSCLK
the SCK pin signal is used as the bit clock for serial-parallel conversion. The value of
(12)
Remark: SCKDIV is in the range 0-255.
Figure 2:
Audio In Clock System and I/O Interface
OSCLK
SCK
WS
SD
div N+1
SCKDIV
div N+1
SER_MASTER
Serial To Parallel
WSDIV
AI domain
LEFT0[31:0]
RIGHT0[31:0]
DDS in Clocks Module
27MHz x 64
Square Wave DDS
7
0
80
32
(e.g. 64xfs)
(e.g. 256xfs)
Converter
LEFT2[31:0]
LEFT3[31:0]
RIGHT1[31:0]
RIGHT2[31:0]
RIGHT3[31:0]
SD1
SD2
SD3
0
LEFT1[31:0]
f
AISCK
f
AIOSCLK
SCKDIV
1
+
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