
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 13: FGPO: Fast General Purpose Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
13-17
14
POLARITY_CLK
R/W
0
Externally selects active clock edge for clk_fgpo via fgpo_clk_pol
0 = rising edge
1 = falling edge
Note: This bit not used in the PNX15xx Series. All FGPO clock
control is in the clock module.
13
OUTPUT_ENABLE_2
R/W
0
Enable output from buffer 2. This bit, along with bit 12 below, start
and stop FGPO DMA activity.
12
OUTPUT_ENABLE_1
R/W
0
Enable output from buffer 1. This bit, along with bit 13 above, start
and stop FGPO DMA activity. If output from only one buffer is
desired, this bit must be used to start/stop DMA.
11
MODE
R/W
0
0 = record mode
1 = message mode
10
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:8
SAMPLE_SIZE
R/W
00
Encodes size of data samples output on fgpo_data:
00 = 8-bit data samples
01 = 16-bit data samples
10 = 32-bit data samples
11 = same as 10 above
Table 3: Fast general purpose output (FGPO) …Continued
Bit
Symbol
Acces
s
Value
Description