- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄42383 > 935271415518 (NXP SEMICONDUCTORS) 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935271415518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SO-8 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 116K |
| 代理商： | 935271415518 |
Philips Semiconductors
Product data
MAX708R/S/T
3 V microprocessor supervisor circuit with
power fail comparator and manual reset
2002 Feb 13
5
TIMING DIAGRAM
On power-up, when VCC reaches 1 V, RESET is guaranteed to be a
logic LOW and RESET is guaranteed to be a logic HIGH.
Event A: VCC rises to the reset threshold voltage, VRST. At this time,
the internal reset delay timer is initiated. RESET and RESET will
remain asserted for the reset delay time, tRST of typically 200 ms
after the supply voltage rises above the reset threshold, VRST.
Event B: At this time, the resets are released. RESET goes HIGH;
while RESET goes LOW. The reset delay time helps to ensure valid
reset signals despite erratic changes in supply voltage.
Events C–E: At Event C, under brown-out conditions, VCC falls
below the reset threshold minus the hysteresis voltage (typically
20 mV), and the reset signal is asserted. As power recovers and
VCC rises above the reset threshold (Event D), it once again
initiates the reset delay time. At Event E, VCC falls below the reset
threshold before the reset delay time has elapsed and reset remains
asserted.
Event F: The VCC rises above the reset threshold again and
remains above the reset threshold for typically 200 ms. At G, the
reset is once again released.
Event H: The MR is externally pulled LOW for longer than 150 ns
(minimum MR pulse width, tMR for VCC = +5 V).
Event I: The manual reset is asserted within 250 ns (maximum MR
to reset out delay time, tMD for VCC = +5V).
Event J: the MR pin returns HIGH. At this point, reset delay timer is
initiated and in typically 200 ms, (at Event K), the reset condition is
released.
Event L: On power-down, when VCC falls below VRST – 20 mV,
RESET and RESET are guaranteed to be asserted until VCC falls
below 1 V.
TIME
RESET
VRST
VCC
VRST – 20 mV
tRST
RESET
MR
SL01812
tMD
tMR
AB
C
D
E
F
G
H
I
J
K
L
Figure 3. Timing diagram.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935271416518 | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 93567-250067 | INTERCONNECTION DEVICE |
| 93570-150300 | INTERCONNECTION DEVICE |
| 93573-150010 | INTERCONNECTION DEVICE |
| 93579-150001 | INTERCONNECTION DEVICE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935271933518 | 制造商:NXP Semiconductors 功能描述:IC D-TYPE POS TRG DUAL 56VFBGA |
| 935271933551 | 制造商:NXP Semiconductors 功能描述:IC D-TYPE POS TRG DUAL 56VFBGA |
| 935271933557 | 制造商:NXP Semiconductors 功能描述:IC D-TYPE POS TRG DUAL 56VFBGA |
| 935271937518 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935271937551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。