參數(shù)資料
型號(hào)： 935269256557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 33/36頁
文件大?。?/td> 145K
代理商： 935269256557
2000 Nov 17
6
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
DMA_WRITE
38
I /O
DMA write strobe input/output (may be congured for active HIGH or active
LOW)
PHY_CTRL[1]
39
I /O
PHY control line input/output (1); note 4
PHY_CTRL[0]
40
I /O
PHY control line input/output (0); note 4
PHY_DATA[0]
41
I /O
PHY data input/output (bit 0); notes 4, 5 and 6
PHY_DATA[1]
42
I /O
PHY data input/output (bit 1); notes 4 and 5
PHY_DATA[2]
43
I /O
PHY data input/output (bit 2); notes 4 and 5
PHY_DATA[3]
44
I /O
PHY data input/output (bit 3); notes 4 and 5
VSS4(P)
45
S
ground 4 for periphery
VDD4(P)
46
S
supply voltage 4 for periphery
PHY_DATA[4]
47
I /O
PHY data input/output (bit 4); notes 4 and 5
PHY_DATA[5]
48
I /O
PHY data input/output (bit 5); notes 4 and 5
PHY_DATA[6]
49
I /O
PHY data input/output (bit 6); notes 4 and 5
PHY_DATA[7]
50
I /O
PHY data input/output (bit 7); notes 4 and 5
VDD5(P)
51
S
supply voltage 5 for periphery
VSS5(P)
52
S
ground 5 for periphery
PHY_SCLK
53
I
PHY system clock input (49.152 MHz)
MICRO_SEL[0]
54
I
microcontroller select (0) input; selects microcontroller interface; note 10
PHY_LREQ
55
O
PHY-Link request output (used to request arbitration or read/write PHY
registers); note 4
PHY_ISO
56
I
PHY isolation barrier input (active LOW). Negated HIGH when the Link and
PHY are directly connected or when bus-holder isolation is used; note 4
MICRO_SEL[1]
57
I
microcontroller select (1) input; selects microcontroller interface; note 10
1394_MODE
58
I /O
note 7
RESET
59
I
asynchronous master reset input to the SAA7356HL (active LOW)
TC
60
reserved for factory testing; for normal operation should be connected to
ground
BT
61
reserved for factory testing; for normal operation should be connected to
ground
MICRO_CS
62
I
microcontroller chip select input (active LOW)
VDD3(C)
63
S
supply voltage 3 for core
VSS3(C)
64
S
ground 3 for core
MICRO_INT
65
O
microcontroller interrupt open-drain output (active LOW)
MICRO_WRITE
66
I
microcontroller write strobe input (active LOW)
MICRO_READ
67
I
microcontroller read strobe input (active LOW)
MICRO_ALE
68
I
microcontroller address latch enable input; note 8
VSS6(P)
69
S
ground 6 for periphery
VDD6(P)
70
S
supply voltage 6 for periphery
MICRO_DATA[0]
71
I /O
microcontroller data input/output [bit 0); note 9
MICRO_DATA[1]
72
I /O
microcontroller data input/output (bit 1); note 9
MICRO_DATA[2]
73
I /O
microcontroller data input/output (bit 2); note 9
MICRO_DATA[3]
74
I /O
microcontroller data input/output (bit 3); note 9
SYMBOL
PIN
TYPE(1)
DESCRIPTION
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