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參數(shù)資料
| 型號(hào)： | 935269132118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 113K |
| 代理商： | 935269132118 |
Philips Semiconductors
Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13
4
FUNCTION TABLE
INPUTS
OUTPUTS
PLL ON/OFF
PWRDWN
CLK
Yn
FBOUT
PLL ON/OFF
L
H
Z
Z1
OFF
L
H
L
Z
Z1
OFF
H
L
H
L
H
L
H
ON
H
L
H
L
H
L
ON
X2
< 20 MHz
Z
Z1
OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FBIN pins.
2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
PLL
37 – PWRDWN
13 – CLK
14 – CLK
36 – FBIN
35 – FBIN
16 – AVDD
3 – Y0
2 – Y0
5 – Y1
6 – Y1
10 – Y2
9 – Y2
20 – Y3
19 – Y3
22 – Y4
23 – Y4
46 – Y5
47 – Y5
44 – Y6
43 – Y6
39 – Y7
40 – Y7
29 – Y8
30 – Y8
27 – Y9
28 – Y9
32 – FBOUT
33 – FBOUT
SW00692
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