
Philips Semiconductors
Product data
SA56600-42
System reset for lithium battery back-up
2001 Jun 19
4
ELECTRICAL CHARACTERISTICS
Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ICC
Supply current
VCC = 5.0 V; VBATT = 3.0 V; IO = 0 mA
–
1.4
2.2
mA
VSAT1
I/O voltage difference 1
VCC = 5.0 V; VBATT = 3.0 V; IO = 1.0 mA
–
0.03
0.05
V
VO1
Output voltage 1
VCC = 5.0 V; VBATT = 3.0 V; IO = 1.0 mA
4.95
4.97
–
V
VO2
Output voltage 2
VCC = 5.0 V; VBATT = 3.0 V; IO = 15 mA
4.75
4.90
–
V
VS
Detection threshold
VCC falling
4.00
4.20
4.40
V
VS
Detection hysteresis
VS = VSH (rising VCC) – VSL (falling VCC)
–
100
–
mA
VRSL
Reset output LOW
VCC = 3.7 V
–
0.2
0.4
V
IRSH
Reset leakage current HIGH
VCC = 5.0 V; VRS = 7.0 V
–
±0.01
±0.1
A
VOPL
Reset assertion
(minimum operating voltage)
VRSL ≤ 0.4 V; VCC falling; RPU = 10 k
–
0.8
1.2
V
VCSL
CS output voltage LOW
VCC = 3.7 V; VBATT = 3.0 V; ICS = 1.0 A
–
0.1
V
VCSH
CS output voltage HIGH
VCC = 5.0 V; VBATT = 3.0 V; ICS = –1.0 A
4.90
–
V
VCSL
CS output voltage LOW
VCC = 5.0 V; VBATT = 3.0 V; ICS = 1.0 A
–
0.2
V
VCSH
CS output voltage HIGH
VCC = 3.7 V; VBATT = 3.0 V; ICS = –1.0 A
VO – 0.1
–
V
VS/T
Detection voltage temperature
characteristic
–40
≤ Tamb ≤ +85
–
±0.05
%/
°C
VBT
Battery back-up threshold
VCC falling
3.15
3.30
3.45
V
VBT(HYS)
Battery back-up hysteresis
VBT(HYS) =
VBTH (VCC rising) – VBTL (VCC falling)
–
100
1.0
mV
VBT/T
Switching voltage temperature
characteristic
–40
≤ Tamb ≤ +85
–
±0.05
%/
°C
IL
Loss current
VCC = 0 V; VBATT = 3.0 V; IO = 0 A
–
0.3
0.5
A
VSAT2
I/O voltage difference 2
VCC = 0 V; VBATT = 3.0 V; IO = 1.0 A
–
0.2
0.3
V
VO3
Output voltage 3
VCC = 0 V; VBATT = 3.0 V; IO = 1.0 A
2.7
2.8
–
V
VO4
Output voltage 4
VCC = 0 V; VBATT = 3.0 V; ICS = 100 A
2.6
2.7
–
V
VREF
Reference voltage (typical)
–
1.25
–
V
IBL
VBATT leakage current
VCC = 5.0 V; VBATT = 0 V
–
0.1
A
IYLO
Y current
VCC = 5.0 V; VBATT = 3.0 V; VY = 0 V
–
150
400
A
tPLH
Y propagation delay time (Note 1)
VY = logic LOW to logic HIGH
–
8.0
20
ns
tPHL
Y propagation delay time (Note 1)
VY = logic HIGH to logic LOW
–
8.0
20
ns
NOTE:
1. Y input rise and fall time less than 6.0 ns. 15 pF capacitance load on CS (Pin 5 to GND).