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參數(shù)資料
| 型號(hào)： | 935269131518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SO-8 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | 935269131518 |
Philips Semiconductors
Product data
SA56600-42
System reset for lithium battery back-up
2001 Jun 19
8
Timing diagram
The Timing Diagram shown in Figure 15 depicts the operation of the
SA56600-42 in its intended application, with a 3.0 V Lithium battery
serving as a backup power source for external SRAM circuitry (see
the Simplified system diagram, Figure 1). Letters indicate events
along the Time axis.
A: At ‘A’, the VCC primary power source is off. As a result of the
backup battery, the CS and VOUT outputs are almost up to the
Lithium battery potential (VB). All other outputs (Y, RESET, and CS)
are at or very near ground potential.
B - C: At ‘B’, the VCC voltage begins to rise. Also the RESET
voltage initially rises but then abruptly returns to a LOW state at ‘C’.
when the VCC voltage reaches the level which activates the internal
bias circuitry and asserts RESET to a logic LOW. This occurs at
approximately 0.8 volts.
D - E: At ‘D’ the internal 3.3 V detection circuit is activated when
VCC voltage rises to 3.3 V. The circuit causes the PNP series pass
switching transistor in the output to activate, connecting the main
power supply voltage (VCC) to the output. This causes the Lithium
battery to be automatically disconnected from VOUT by back-biasing
the Schottky diode. As a result, CS and VOUT begin to rise with VCC.
E: At ‘E’, VCC has risen to the upper detection threshold (VS plus
hysteresis) as sensed by the device’s internal 4.2 V detection circuit.
This event signals that the output voltage is adequate to support full
operation of the associated external computer circuitry. RESET goes
HIGH, allowing the microprocessor circuitry to operate.
Simultaneously, CS also goes HIGH, signaling the SRAM to start
receiving data. CS goes LOW as a result of Y simultaneously being
at a LOW state.
Y controls the CS output. As long as Y is LOW, the CS output is
enabled.
F: As VCC continues to rise, RESET, CS, and VOUT also continue to
rise. Just before ‘F’, Y is asserted HIGH by the microprocessing
circuitry. This causes CS to change from a LOW state to a HIGH
state. Following ‘F’ the microprocessing circuitry is signaling Y
through repetitive cycles. This causes CS to also cycle, but has no
effect on the battery circuit.
G: At ‘G’, the VCC voltage begins to fall. As a result RESET, CS,
and VCC fall.
H: When the VCC voltage falls to VS (4.2 V) it is detected by the
internal 4.2 V detector circuit. The detector circuit forces RESET and
CS LOW, deselecting the SRAM and stopping data storage and
retrieval. The PNP series pass switching transistor disconnects the
primary input source voltage from the output, transferring the SRAM
to the backup battery. In addition, because Y is already at a LOW
state, CS rises abruptly close to VS followed by a continued fall to
VB (Lithium battery potential), following VCC.
J: At ‘J’, VOUT has also fallen with VCC to a level that is now
dictated by the Lithium battery potential. The Lithium battery is now
maintaining the VOUT voltage to preserve the SRAM data.
K - L: As the VCC voltage falls to a level which no longer allows the
internal bias circuitry to remain active, the assertion of RESET can
no longer be maintained. RESET rises slightly, then falls to ground
as VCC falls to ground.
M: Y is asserted HIGH again by the microprocessor, but because
VCC is below VS, CS remains HIGH and CS remains LOW,
preventing the SRAM from being selected.
TIME
AB C
DE F
G H
J
K
0
L
0
VRSH
VO1, O2
VCSH
VCSL
VO3, O4
VCSL
≤VB
VRSL
VOUT
CS
RESET
Y
VCC
5.0
VS
VB
SL01341
VOPL
VCSH
Figure 15. Timing diagram.
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