參數(shù)資料
型號(hào)： 935268498551
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24
封裝： 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24
文件頁數(shù)： 7/28頁
文件大?。?/td> 278K
代理商： 935268498551
Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
15
Table 6. Kn values for the fractional divider
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Kn
0
1
0
1
0
2
0
1
3
0
1
0
4
–
…
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2966702
–
…
1
0
4194302
1
4194303
2.4
B-word register
Table 7. B-word, length 24 bits
Last IN
<21>
<20>
<19>
<18>
<17>
<16>
<15>
<14>
<13>
<12>
<11>
<10>
<9>
<8>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address
Reference divider ratio Rn
Reset
bit
Power Down
RF Divider integer ratio N
0
1
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
PDref
IF
RF
N8
N7
N6
N5
N4
N3
N2
N1
N0
Default:
0
1
0
1
0
1
0
1
0
1
0
1
0
B-word address
Fixed to 01
R-Divider
R0..R9, Reference divider values, see section “characteristics” for allowed divider ratios.
Reset bit
1
→ Pdref : powers down (=resets) the reference divider
Power-down
See Truth Table 9
N-Divider
Nn sets the integer part of the RF divider ratio, see section “characteristics” for allowed ratios.
2.4.1
The RF divider <B8:B0>
Programming the RF divider to obtain the desired VCO output frequency is done by programming the B-word followed by the A-word. The
integer divider bits N<8:0> are in the B-word, whereas the fractional divider bits Kn<22:1> are in the A-word. Allowable integer division ratios are
shown in Table 8. The N value, from Equation (2), is simply the whole number of times the reference frequency goes into the desired VCO
output frequency. Recall that the reference frequency for the RF loop is not reduced prior to the phase detector. In other words, the frequency at
the input of the REFin is the comparison frequency.
N
+
fVCO
f
ref
*
MODULO
fVCO
f
ref
f
ref
(2)
N
+ 900 MHz
19.68 MHz
*
MODULO
900 MHz
19.68 MHz
N
+ 45.7317073170...– 14.4
19.68
+ 45
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