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參數(shù)資料
| 型號： | 935268498551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24 |
| 封裝： | 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 278K |
| 代理商： | 935268498551 |
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Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
14
2.1
Data format
Each of the 4 word registers contains 24 programmable bits. Data is serially clocked in on the rising edge of each clock pulse with the
LSB first in, and MSB last in.
Table 3. Format of programmed data
LAST IN
MSB
SERIAL PROGRAMMING FORMAT
FIRST IN
LSB
p23
p22
p21
p20
.. / ..
p1
p0
2.2
Register addressing
Table 4. Register addressing
Bit
<23>
<22>
<21>
A-word address
0
x
B-word address
0
1
x
C-word address
1
0
x
D-word address
1
0
Notice that the register addresses are the MSB in each word; thus, the last to be clocked into the registers.
2.3
A-word register
Table 5. A-word, length 24 bits
Last IN
<21>
<20>
<19>
<18>
<17>
<16>
<15>
<14>
<13>
<12>
<11>
<10>
<9>
<8>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address
Fractional ratio Kn
0
K22
K21
K20
K19
K18
K17
K16
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
Default :
0
1
0
1
0
1
0
1
0
1
0
1
A word address
Fixed to 00.
Fractional ratio select
Kn sets the fractional part of the total division ratio. To avoid limit cycles the K0 bit is internally set to “1”
2.3.1
The fractional multiplier <A21:A0>
The A-word register is dedicated for programming the RF loop, fractional multiplier (the sigma-delta modulator) which has an effective resolution
of 22 bits. The modulator works with 23 bits, Kn<22:0>. However, this K0 bit is set to ‘1’ internally to avoid limit cycles (cycles of less than
maximum length). This leaves 22 bits (Kn<22:1>) available for external programming. Refer to Table 6.
Calculating the desired VCO output frequency can be easily accomplished by using the following equation, Equation (1).
fVCO + fref N )
2
Kn <22:1>
) 1
223
(1)
where fref is the reference frequency at the REF input pin and N is the integer multiplier. Kn, once again, is the fractional multiplier.
Example:
Determine the Kn value required for generating a VCO frequency of 2100 MHz with a reference frequency of 19.68 MHz.
Kn<22:1>
+
fVCO
f
ref
–N
223
2
Kn<22:1>
+
2100 MHz
19.68 MHz
–106
223
2
+ 2966702
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