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參數(shù)資料
| 型號： | 935268498518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24 |
| 封裝： | 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 278K |
| 代理商： | 935268498518 |
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Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
16
Table 8. Allowable integer values (N) for the RF divider
<B8>
<B7>
<B6>
<B5>
<B4>
<B3>
<B2>
<B1>
<B0>
N
0
1
0
1
33
—
…
—
…
—
…
—
…
1
0
1
509
2.4.2
Power–down <B10:B9>
If the chip is programmed while in power-up mode, the loading of the A-word and of the N values in the B-word are synchronized to the RF
divider output pulse. The data takes effect internally on the second falling edge of the RF divider output pulse after STROBE has gone high at
the end of the A-word. STROBE does not need to be held high until that second falling edge of the RF divider output pulse has occurred.
If the chip is programmed while in power-down mode, this synchronization scheme is disabled. The fully static CMOS design uses virtually no
current when the bus is inactive. It can always capture new programmed data, even during power-down.
To take advantage of the program register pre-loading capability while the device is in power-down mode, the B-word needs to be sent a second
time (i.e. again, after the A-word), with the PD bits now programmed for power-up. If power-up mode is to be controlled by hardware, the PON
signal must be toggled only after the A-word has been sent and STROBE has gone high and then low.
When the synthesizer is reactivated after power-down mode, the IF and reference dividers are synchronized to avoid random phase errors on
power-up. There is no power-up synchronization between the RF divider and the reference clock. However, after power-up, there is a delay of
four edges (i.e. 1.5 cycles) of the output clock of the reference divider before the RF phase detector is activated. That means the reference
divider must be powered up for the RF phase detector to become active.
When initially applying or re-applying power to the chip, an internal power-up reset pulse is generated which sets the programming-words to
their default values and also resets the sigma-delta modulator to its “all-0” state. It is also recommended that the D-word be manually reset to all
zeros, following initial power-up, to avoid unknown states.
Table 9. Power-down Truth Table
PON
IF
<B10>
RF
<B9>
IF
RF
0
OFF
0
1
OFF
ON
0
1
0
ON
OFF
0
1
ON
1
0
ON
1
0
1
ON
OFF
1
0
OFF
ON
1
OFF
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