參數(shù)資料
型號(hào)： 935268498518
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24
封裝： 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 278K
代理商： 935268498518
Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
8
1.0
FUNCTIONAL DESCRIPTION
Frequency synthesizers, such as Philips Semiconductors’ SA8028,
are a crucial part of Phase Locked Loops (PLL) for both voice and
data devices used in communications. Five components make up
the basic PLL (see Figure 4). A very stable, low frequency, signal
source (typically a temperature controlled crystal oscillator TCXO_)
is used as a reference to the system. A second signal source
(typically a VCO) is used to generate the desired output frequency.
A phase/frequency detector (PFD) is used to compare the
phase/frequency error between the two signals. A loop filter (LPF)
rejects undesired noise while also integrating the PFD output current
to drive the VCO with the necessary tuning voltage, and a divider in
the feedback path is used to down-convert the VCO output
frequency to the reference frequency for comparison. The SA8028
is a dual synthesizer that integrates programmable dividers,
programmable charge pumps and phase comparators to be
implemented as part of RF and IF PLLs. The RF synthesizer
operates at VCO input frequencies up to 2.5 GHz, while the IF
synthesizer operates at VCO input frequencies up to 760 MHz.
SR02370
PFD
Φ
TCXO
LPF
INTEGRATOR
VCO
1
N
DIVIDER
+
N(τ)
Figure 4.
PLL block diagram.
1.1
RF Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed
(AC-coupled) to one of the inputs while the other one is AC grounded.
The pre-amplifier has a high input impedance, dominated by pin and
pad capacitance. The bipolar divider is fully programmable. For
allowable division ratios, see the “characteristics” table.
During each RF divider cycle, one divider output pulse is generated.
The positive edge of this pulse drives the phase comparator, the
negative edge drives the sigma-delta modulator which is of 2nd
order and has an effective resolution of 22 bits. Internally, the
modulator works with 23 fractional bits K<22:0>, but the LSB (bit K0)
is set to ‘1’ internally to avoid limit cycles (cycles of less than
maximum length). This leaves 22 bits (K<22:1>) available for
external programming.
Under these conditions (2nd order modulator, 23 fractional bits,
K0 = ‘1’), all possible sigma-delta sequences are 2*223 divider
cycles long, which is the maximum length. The noise shaping
characteristic is +20 dB/dec for offset frequencies up to approx.
fCOMP/5, which needs to be cancelled by a closed-loop transfer
function of sufficient high order. The output of the sigma-delta
modulator is 2 bits, which are added to the integer RF division ratio
N, such that the momentary division ratios range from
(N–1) to (N+2) in steps of 1.
1.2
IF divider
The IFin input drives a pre-amplifier to provide the clock to the first
divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The divider consists of a
fully programmable bipolar prescaler followed by a CMOS counter.
The allowable divide ratios are from 128 to 16383 (C-word bits
<21:8>). Table 14 shows all the possible values that can be
programmed into the C-Word for the IF divider.
1.3
Reference divider (see Figure 5)
The IF phase detector’s reference input is an integer ratio of the
reference frequency. The reference divider chain consists of a
bipolar input buffer followed by a CMOS divider and a 3-bit binary
counter (SA register). The allowable divide ratios, R, are from 4 to
1023 (B-word bits <21:12>) when the 3-bit binary counter (C-word
bits <2:0>) is set to all zeros, SA = 000. The 3-bit SA register
determines which of the 5 divider outputs (refer to Table 12) is
selected as the IF phase detector input (see Figure 5). For the RF
synthesizer, the output of the reference input buffer is routed directly
(not reference divider) to the input of the RF phase detector.
SR02294
DIVIDE BY R
/2
SA=”100”
SA=”011”
SA=”010”
SA=”001”
SA=”000”
TO RF PHASE
DETECTOR
TO IF PHASE
DETECTOR
REFERENCE
INPUT BUFFER
REFERENCE
INPUT
Figure 5.
Reference divider.
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