參數(shù)資料
型號(hào)： 935264533557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： SOT-317, MQFP-100
文件頁(yè)數(shù)： 16/43頁(yè)
文件大小： 254K
代理商： 935264533557
1999 March 01
23
Philips Semiconductors
Product specication
Single chip DVB-C channel receiver
VES1820X
ENADAPT
When ENADAPT is set to 0, the adaptation algorithm is inhibited. The equalizer is
running with the current value of the coefficients. When ENADAPT=1 (default), the
coefficients of the equalizer are continuously adjusted.
ENEQUAL
When ENEQUAL=0, the equalization function is inhibited. The equalizer
coefficients are fixed to their initialization values. The default is ENEQUAL = 1.
DFE
DFE determines wether the equalizer is configured as a linear transversal
equalizer (DFE=0) or a decision feedback equalizer (DFE=1, default).
8. EQSTEP
07
16
READ/WRITE
EQST1[2:0]
EQST1[2:0] sets the convergence step of the adaptation algorithm during the
acquisition phase. The higher EQST1[2:0] is, the higher the step is. Default value
is 2.
EQST2[2:0]
EQST2[2:0] sets the convergence step of the adaptation algorithm during the
tracking phase.The higher EQST2[2:0] is, the higher the step is. Default value is 3.
9. MSETH
08
16
READ/WRITE
MSETH[7:0] MSETH[7:0] is the threshold value used to switch from the acquisition phase to the
tracking phase. MSETH[7:0] must be set as follows (decimal values) :
MSETH[7:0]
Modulation
162
16-QAM
116
32-QAM
67
64-QAM (default)
52
128-QAM
35
256-QAM
10. AREF
09
16
READ/WRITE
AREF[7:0]
AREF[7:0] is a reference parameter that optimizes the equalizer convergence
during the acquisition phase. AREF[7:0] must be set as follows (decimal values) :
AREF[7:0]
Modulation
145
16-QAM
150
32-QAM
106
64-QAM (default)
126
128-QAM
107
256-QAM
11. BDR_LSB
0A
16
READ/WRITE
BDR_LSB
8 LSB bits : BDR[7:0] of the BAUD rate frequency to program.
12. BDR_MID
0B
16
READ/WRITE
BDR_MID
8 MID bits : BDR[15:8] of the BAUD rate frequency to program.
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