參數(shù)資料
型號(hào)： 935264477112
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 無(wú)繩電話(huà)/電話(huà)
英文描述： TELEPHONE SPEECH CKT, PDSO40
封裝： PLASTIC, SOT-158, VSOP-40
文件頁(yè)數(shù)： 6/39頁(yè)
文件大?。?/td> 205K
代理商： 935264477112
1999 Apr 08
14
Philips Semiconductors
Product specication
Speech and loudspeaker amplier IC with
auxiliary inputs/outputs and analog multiplexer
TEA1097
Loudspeaker channel
Fig.8 Loudspeaker channel.
The pin numbers given in parenthesis refer to the TEA1097H.
handbook, full pagewidth
MGL394
DYNAMIC
LIMITER
VOLUME
CONTROL
I
V
I
DLC
LSAO
GALS
VOL
HFRX
14
(11)
16
(12)
11
(8)
7
(1)
27
(23)
VBB
RGALS
CGALS
CLSAO
CDLC
RVOL
to
logic
LOUDSPEAKER AMPLIFIER: PINS HFRX, GALS AND LSAO
The TEA1097 has an asymmetrical input for the
loudspeaker amplifier with an input resistance of 20 k
between pins HFRX and GND. It is biased at two diodes
voltage. The input stage can accommodate signals up to
580 mV (RMS) at room temperature for 2% of THD.
The rail-to-rail output stage is designed to power a
loudspeaker down to 8
connected as a single-ended
load (between pins LSAO and GND). When the circuit is
externally supplied, the maximum output power is equal to
280 mW (typ.) for 6 V applied to pin ESI.
The gain of the loudspeaker amplifier can be adjusted from
0 to 35 dB to suit specific application requirements.
The gain from HFRX to LSAO is proportional to the value
of RGALS and equals 28 dB with RGALS = 255 k.
A capacitor connected in parallel with RGALS is
recommended and provides a first-order low-pass filter.
VOLUME CONTROL (PIN VOL)
The loudspeaker amplifier gain can be adjusted with the
potentiometer RVOL. A linear potentiometer can be used to
obtain logarithmic control of the gain at the loudspeaker
amplifier. Each 1.9 k
increase of RVOL results in a gain
loss of 3 dB.
DYNAMIC LIMITER (PIN DLC)
The dynamic limiter of the TEA1097 prevents clipping of
the loudspeaker output stage and protects the operation of
the circuit when the supply voltage at VBB falls below 2.7 V.
Hard clipping of the loudspeaker output stage is prevented
by rapidly reducing the gain when the output stage starts
to saturate. The time in which gain reduction is effected
(clipping attack time) is approximately a few milliseconds.
The circuit stays in the reduced gain mode until the peaks
of the loudspeaker signals no longer cause saturation.
The gain of the loudspeaker amplifier then returns to its
normal value within the clipping release time (typically
100 ms). Both attack and release times are proportional to
the value of the capacitor CDLC. The total harmonic
distortion of the loudspeaker output stage, in reduced gain
mode, stays below 1% up to 10 dB (min.) of input voltage
overdrive [providing VHFRX is below 580 mV (RMS)].
When the supply voltage drops below an internal threshold
voltage of 2.7 V, the gain of the loudspeaker amplifier is
rapidly reduced (approximately 1 ms). When the supply
voltage exceeds 2.7 V, the gain of the loudspeaker
amplifier is increased again. By forcing a level lower than
0.2 V on pin DLC, the loudspeaker amplifier is muted.
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