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參數(shù)資料
| 型號(hào)： | 935264405118 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | 935264405118 |
Philips Semiconductors
Product specification
PCK2510S
50–150 MHz 1:10 SDRAM clock driver
2001 Feb 02
8
CHARACTERISTICS CURVES
ANALOG
SUPPL
Y
CURRENT
(mA)
CLOCK FREQUENCY (MHz)
SW00435
AVCC = VCC = 3.3 V
Tamb = 25 °C
0
1
2
3
4
5
6
7
8
30
40
50
60
70
80
90
100
11
0
120
130
140
150
Figure 3. Analog supply current vs. clock frequency
SUPPL
Y
CURRENT
(mA)
CLOCK FREQUENCY (MHz)
SW00434
AVCC = VCC = 3.3 V
Tamb = 25 °C
0
10
20
30
40
50
60
70
80
90
100
30
40
50
60
70
80
90
100
11
0
120
130
140
150
Figure 4. Supply current vs. clock frequency
0
50
100
150
200
PEAK-TO-PEAK
JITTER
(ps)
CLOCK FREQUENCY (MHz)
SW00433
AVCC = VCC = 3.3 V
C(LF) = 12 pF; Tamb = 25 °C
50
100
133
150
Figure 5. Peak-to-peak jitter vs. clock frequency
0
50
100
150
200
50
60
70
80
90
100
110
120
130
140
CYCLE-TO-CYCLE
JITTER
(ps)
CLOCK FREQUENCY (MHz)
SW00432
AVCC = VCC = 3.3 V
C(LF) = 12 pF; Tamb = 25 °C
Figure 6. Cycle-to-cycle jitter vs. clock frequency
PHASE
OFFSET
(ps)
DELAY LENGTH (ns)
SW00439
–40
–20
0
20
40
60
80
100
02
46
8
10
VCC = 3.3 V; C(LF) = 30 pF; f = 100 MHz
Figure 7. Phase offset vs. delay length
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