1999 Feb 17
15
Philips Semiconductors
Product specication
Cordless telephone, answering machine
line interface
UBA1707
Fig.13 Loudspeaker channel.
Bit names are given in italics.
handbook, full pagewidth
MGK713
LSAI1
LSAI2
2Vd
LSPD
LSA2
LSA1
0.5VCC
DYNAMIC LIMITER
VOLUME CONTROL
VCC
UBA1707
DLCI
LSPD
VOL0
TO
VOL2
DLC
LSPGND
LSAO
3
VI
IV
LSP
CDLC
CLSAO
DYNAMIC LIMITER (PIN DLC; BIT DLCI)
The dynamic limiter of the UBA1707 prevents clipping of
the loudspeaker output stage and protects the operation of
the circuit when the supply voltage at VCC falls below
2.7 V.
Hard clipping of the loudspeaker output stage is prevented
by rapidly reducing the gain when the output stage starts
to saturate. The time in which gain reduction is effected
(clipping attack time) is approximately a few milliseconds.
The circuit stays in the reduced gain mode until the peaks
of the loudspeaker signals no longer cause saturation.
The gain of the loudspeaker amplifier then returns to its
normal value within the clipping release time (typically
250 ms). Both attack and release times are proportional to
the value of the capacitor CDLC. The total harmonic
distortion of the loudspeaker output stage, in reduced gain
mode, stays below 5% up to 10 dB (minimum) of input
voltage overdrive [providing VLSAI is below
500 mV (RMS)].
When the supply voltage drops below an internal threshold
voltage of 2.7 V, the gain of the loudspeaker amplifier is
rapidly reduced (approximately 1 ms). When the supply
voltage exceeds 2.7 V, the gain of the loudspeaker
amplifier is increased again.
The hard clipping of the dynamic limiter can be inhibited by
setting the DLCI bit at logic 1, via the serial interface.
The dynamic limiter is no longer supplied by setting the
LSPD bit at logic 1. In this case, the CDLC capacitor charge
is maintained to allow the gain of the loudspeaker amplifier
to return to its nominal value as soon as the loudspeaker
channel is supplied again.
VOLUME CONTROL (BITS VOL0, VOL1 AND VOL2)
The loudspeaker amplifier voltage gain can be reduced in
steps of 3 dB via the serial interface (via bits VOL0, VOL1
and VOL2). These bits provide 7 steps of voltage gain
adjustment. The voltage gain is maximum when all bits are
at logic 1 and is reduced by 21 dB when all bits are at
logic 0.