參數(shù)資料
型號(hào)： 935263971112
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
封裝： PLASTIC, SOT-136, SO-28
文件頁(yè)數(shù)： 37/38頁(yè)
文件大?。?/td> 287K
代理商： 935263971112
1999 Feb 17
8
Philips Semiconductors
Product specication
Cordless telephone, answering machine
line interface
UBA1707
The DC line current flowing into the set is determined by
the exchange supply voltage (Vexch), the feeding bridge
resistance (Rexch), the DC resistors of the telephone line
(Rline) and the set (RSET), the reference voltage (Vref) and
the voltage introduced by the transistor (TNSW) used as
line interrupter (see Fig.5). With a line current below Ilow
(8 mA with ZSET = 619 ), the internal reference voltage
(Vref) is automatically adjusted to a lower value. This
means that more sets can operate in parallel with DC line
voltages (excluding the polarity guard) down to 1.2 V.
At line current below Ilow, the circuit has limited transmit
and receive levels. This is called the low voltage area.
Figure 6 shows in more details how the UBA1707, in
association with some external components, manages the
line interrupter (TNSW external transistor).
In on-hook conditions (voltage at pin EHI is LOW), the
voltage at pin LCC is pulled-up to the supply voltage level
(VCC) to turn off the TPDARL transistor. As a result, because
of the RPLD resistor, the TNSW and TNON-HOOK transistors
are switched off. The TNON-HOOK transistor disconnects
the RLVI resistor from the LN line terminal in order to
guarantee a high on-hook impedance.
In off-hook conditions (voltage at pin EHI is HIGH), an
operational amplifier drives (at pin LCC) the base of
TPDARL which forms a current amplifier structure in
association with TNSW. The line current flows through
TNSW transistor. The TNON-HOOK transistor is forced into
deep saturation. A virtual ground is created at pin LVI
because of the operational amplifier. A DC current (ILVI) is
sourced from pin LVI into the RLVI resistor in order to
generate a voltage source. Thus the voltage between pin
GND and the negative line terminal (LN
) becomes:
VCE (TNSW)=RLVI × ILVI +VCE (TNON-HOOK) RLVI × ILVI
The voltage Vline between the line terminals LN+ and LN
can be calculated as follows:
Vline Vref +RSLPE × (Iline IZSET)+VCE (TNSW)
Where:
Iline = line current
IZSET = current flowing through ZSET.
相關(guān)PDF資料
PDF描述
935263971118 SPECIALTY TELECOM CIRCUIT, PDSO28
08-040831 OUTLINE AUTO - TANGING MEGAPAC
08-040831-C OUTLINE AUTO - TANGING MEGAPAC
08-040921 OUTLINE MINI MEGAPAC STANDARD CHASSIS
08-040921-D OUTLINE MINI MEGAPAC STANDARD CHASSIS
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