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參數(shù)資料
| 型號： | 935263912557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大小： | 277K |
| 代理商： | 935263912557 |
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Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
23
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHY packet first quadlet
11102
00002
SV00265
31 30
Figure 22. PHY Packet Receive Format
For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified
and is not included.
12.5.2.5
Transaction data confirmation formats
After a packet from one of the queues has been transmitted, the asynchronous transmitter assembles a confirmation (see Figure 23) which is
used to confirm the result of the transmission to the higher layers. Separate confirmations are assembled for request and response
transmissions. Request confirmations are written into the receiver request queue and response confirmations are written into the receiver
response queue.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
conf
destinationID
tLabel
3130
10002
002
SV00821
Figure 23. Request and response confirmation format
Table 7.
Confirmation codes
CODE1
DESCRIPTION
0
Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).
1
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete
(transaction complete).
2
Non-broadcast packet transmitted; addressed node returned an acknowledge pending.
4
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries
(transaction complete).
D16
Acknowledge data error received (transaction complete).
E16
Acknowledge type error received (transaction complete).
NOTE:
1. All other codes are reserved.
For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV
layer logic.
相關PDF資料 |
PDF描述 |
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| 935263912551 | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 08-1101-00 | DREHSCHALTER 1POL 12STELLUNGEN |
| 08-1260-00 | ************GESTRICHEN************ |
| 08-1341-00 | DREHSCHALTER 3POL 4STELLUNGEN |
| 08-2101-00 | DREHSCHALTER 2POL 12STELLUNGEN |
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