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參數(shù)資料
| 型號： | 935263687551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 6 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PBGA64 |
| 封裝： | PLASTIC, LFBGA-64 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 170K |
| 代理商： | 935263687551 |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
3
5.0
PIN DESCRIPTION
PIN NUMBER
PIN SYMBOL
I/O
NAME AND FUNCTION
1
RESET–
I*
Phy reset, active LOW
2
LPS
I*
Link Layer Controller (LLC) power status
3
LREQ
I*
Link request from controller
4
DVDD
I*
Should be connected to the LLC VDD supply when a 5V LLC is connected to the
Phy, and should be connected to the Phy DVDD when a 3V LLC is used.
5, 6, 19, 20
DVDDD
I
Digital circuit power
7
PD
I*
Device power down input
8, 10, 17, 18, 63, 64
DGND
–
Digital circuit ground
9
SYSCLK
O*
49.152 MHz clock to link controller
11, 12
CTL[0:1]
I/O*
Link interface bi-directional control signals
13, 14, 15, 16
D[0:3]
I/O*
Link interface bi-directional data signals
22, 21
TESTM[1:2]
I*
Test/Mode Control pins
11 =1394–1995 mode
10 = 1394a mode
00/01 = Reserved
23
CPS
I
Cable power status
24, 25, 51, 55
AVDD
–
Analog circuit power
26, 32, 41, 49, 50, 61
AGND
–
Analog circuit ground
27
C/LKON
I/O*
Bus/Isochronous Resource Manager capable input, or LINK-ON signal output
30, 29, 28
PC[0:2]
I*
Power class bits 0 through 2 inputs
31
CNA
O*
Cable Not Active output
36, 40, 45
TPA[1:3]+
I/O
Port n cable pair A, positive signal
35, 39, 44
TPA[1:3]–
I/O
Port n cable pair A, negative signal
34, 38, 43
TPB[1:3]+
I/O
Port n cable pair B, positive signal
33, 37, 42
TPB[1:3]–
I/O
Port n cable pair B, negative signal
46, 47, 48
TPBIAS[1:3]
O
Cable termination voltage supplies
52, 53
PLLGND
–
PLL circuit ground
54
FILTER
I/O
PLL external filter capacitor
56
XI
I
Crystal oscillator connection
57
XO
O
Crystal oscillator connection
58
PLLVDD
–
PLL circuit power
59, 60
R[0:1]
–
External current setting resistor
62
ISO–
I*
Link interface isolation status input
NOTE:
* Indicates 5V tolerant structure.
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