參數(shù)資料
型號： 935263366112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 31/80頁
文件大?。?/td> 446K
代理商： 935263366112
1997 Dec 15
37
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
14 INTERRUPT SYSTEM
The P83C528 contains the same interrupt structure as the
PCB80C51BH, but with a seven-source interrupt structure
with two priority levels (see Fig.19).
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in TCON SFR. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON. When an
external interrupt is generated, the corresponding request
flag is cleared by the hardware when the service routine is
vectored to, only if the interrupt was transition-activated. If
the interrupt was level-activated then the interrupt request
flag remains set until the external interrupt pin INTx goes
high.
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical 'OR' of
RI and TI. Neither of these flags is cleared by hardware.
The service routine will normally have to determine
whether it was RI or TI that generated the interrupt, and the
bit will have to be cleared by software.
The Timer 2 Interrupt is generated by the logical OR of TF2
and EXF2. Neither of these flags is cleared by hardware.
In fact the service routine may have to determine whether
it was TF2 or EXF2 that generated the interrupt, and the bit
will have to be cleared by software.
An additional (third) external interrupt is available, if Timer
2 is not used as timer/counter or if Timer 2 is used in baud
rate generator mode. That external interrupt 2 is falling
edge triggered. It shares the Timer 2 interrupt vector,
interrupt enable and interrupt priority bits. If bit
T2CON.3/EXEN2 = 1, a HIGH-to-LOW transition at pin
P1.1/T2EX sets the interrupt request flag T2CON.6/EXF2
and can be used to generate an external interrupt.
The I2C interrupt is generated by SI in S1INT. This flag has
to be cleared by software. All of the bits that generate
interrupts can be set or cleared by software, with the same
result as though they had been set or cleared by hardware,
with the exception of the I2C interrupt request flag SI,
which cannot be set by software. That is, interrupts can be
generated or pending interrupts can be cancelled in
software.
Fig.19 P83C528 Interrupt Sources.
handbook, halfpage
MBC481 - 1
IE1
0
1
IE0
0
1
interrupt
sources
INT0
TF2
EXF2
SI
TF0
INT1
TF1
TI
RI
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