參數(shù)資料
型號(hào)： 935263366112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 19/80頁(yè)
文件大?。?/td> 446K
代理商： 935263366112
1997 Dec 15
26
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
11.2
Timer 2
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two
SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload
register. Like Timer 0 and 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in the
T2CON SFR. The timer has three operating modes: 'capture', 'autoload' and 'baud rate generator', which are selected
by bits in the T2CON SFR (see Table 9).
Table 9
Timer 2 operating modes
11.2.1
TIMER 2CONTROL REGISTER (T2CON)
Table 10 Timer 2 Control register (address C8H)
Table 11 Description of the T2CON bits
RCLK + TCLK
CP/RL2
TR2
MODE
0
1
16-bit automatic reload
0
1
16-bit capture
1
X
1
baud rate generator
X
0
OFF
76543210
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
MNEMONIC
POSITION
FUNCTION
TF2
T2CON.7
Timer 2 overow ag: set by a Timer 2 overow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled,
TF2 = 1 (see EXF2).
EXF2
T2CON.6
Timer 2 external ag: set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to Timer 2 interrupt routine.
RCLK
T2CON.5
Receive clock ag: when set, causes the Serial Port to use Timer 2 overow pulses for
its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overows to be used for
the receive clock.
TCLK
T2CON.4
Transmit clock ag: when set, causes the Serial Port to use Timer 2 overow pulses
for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overows to be used
for the transmit clock.
EXEN2
T2CON.3
Timer 2 external enable ag: when set, allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control: a logic 1 starts Timer 2. A logic 0 stops Timer 2.
C/T2
T2CON.1
Timer/counter select: 0 = internal timer (OSC/12). 1 = external event counter (falling
edge triggered).
CP/RL2
T2CON.0
Capture/reload ag: when set, capture will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overows or negative
transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored
and the timer is forced to reload upon overow.
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