- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24676 > 935263316026 (NXP SEMICONDUCTORS) LIQUID CRYSTAL DISPLAY DRIVER, UUC56 PDF資料下載
參數(shù)資料
| 型號： | 935263316026 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC56 |
| 封裝： | DIE |
| 文件頁數(shù)： | 14/43頁 |
| 文件大小： | 327K |
| 代理商： | 935263316026 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
1997 Apr 01
21
Philips Semiconductors
Product specication
LCD column driver for dot matrix graphic
displays
PCF8579
9
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
9.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the stop condition (P).
9.3
System conguration
A device transmitting a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message flow is the ‘master’ and the devices
which are controlled by the master are the ‘slaves’.
9.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
Fig.13 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
相關PDF資料 |
PDF描述 |
|---|---|
| 933964690623 | F/FAST SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 0570360000 | 24 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 933966340235 | 300 mA, 60 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236AB |
| 933966340215 | 300 mA, 60 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236AB |
| 933967880112 | HCT SERIES, OCTAL 1-BIT DRIVER, INVERTED OUTPUT, PDIP20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復。