參數(shù)資料
型號(hào)： 935263156557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 62/76頁(yè)
文件大?。?/td> 567K
代理商： 935263156557
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
65
11.
AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10% (EBx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency)
VDD = 5 V ± 10% (EFx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency)
Tamb = 0 °C to +70 °C, tCLK min = 63 ns for P8xC557E4EBx
Tamb = –40 °C to +85 °C, tCLK min = 63 ns for P8xC557E4EFx
C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified.
12MHz CLOCK
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/tCLK
60
System clock frequency
3.5
16
MHz
tLHLL
60
ALE pulse width
127
85
2tCLK–40
ns
tAVLL
60
Address valid to ALE LOW
43
23
tCLK–40
ns
tLLAX
60
Address hold after ALE LOW
53
33
tCLK–30
ns
tLLIV
60
ALE LOW to valid instruction in
234
150
4tCLK–100
ns
tLLPL
60
ALE LOW to PSEN LOW
53
33
tCLK–30
ns
tPLPH
60
PSEN pulse width
205
143
3tCLK–45
ns
tPLIV
60
PSEN LOW to valid instruction in
145
83
3tCLK–105
ns
tPXIX
60
Input instruction hold after PSEN
0
ns
tPXIZ
60
Input instruction float after PSEN
59
38
tCLK–25
ns
tAVIV
60
Address to valid instruction in
312
208
5tCLK–105
ns
tPLAZ
60
PSEN LOW to address float
10
ns
Data Memory
tAVLL
61, 62
Address valid to ALE LOW
43
23
tCLK–40
ns
tLLAX
61, 62
Address hold after ALE LOW
48
28
tCLK–35
ns
tRLRH
61
RD pulse width
400
275
6tCLK–100
ns
tWLWH
62
WR pulse width
400
275
6tCLK–100
ns
tRLDV
61
RD LOW to valid data in
252
148
5tCLK–165
ns
tRHDX
61
Data hold after RD
0
ns
tRHDZ
61
Data float after RD
97
55
2tCLK–70
ns
tLLDV
61
ALE LOW to valid data in
517
350
8tCLK–150
ns
tAVDV
61
Address to valid data in
585
398
9tCLK–165
ns
tLLWL
61, 62
ALE LOW to RD or WR LOW
200
300
138
238
3tCLK–50
3tCLK+50
ns
tAVWL
61, 62
Address valid to WR LOW or RD LOW
203
120
4tCLK–130
ns
tQVWX
62
Data valid to WR transition
33
13
tCLK–50
ns
tQVWH
62
Data before WR
433
288
7tCLK–150
ns
tWHQX
62
Data hold after WR
33
13
tCLK–50
ns
tRLAZ
61
RD low to address float
0
ns
tWHLH
61, 62
RD or WR HIGH to ALE HIGH
43
123
23
103
tCLK–40
tCLK+40
ns
UART Timing – Shift Register Mode (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80pF)
tXLXL
64
Serial port clock cycle time
1.0
0.75
12tCLK
s
tQVXH
64
Output data setup to clock rising edge
700
492
10tCLK–133
ns
tXHQX
64
Output data hold after clock rising edge
50
8
2tCLK–117
ns
tXHDX
64
Input data hold after clock rising edge
0
ns
tXHDV
64
Clock rising edge to input data valid
700
492
10tCLK–133
ns
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