參數(shù)資料
型號(hào)： 935263122557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 38/76頁(yè)
文件大?。?/td> 567K
代理商： 935263122557
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
43
6.11.3
Power-down Mode
The instruction that sets PCON.1 is the last executed prior to going
into the Power-down Mode. Once in Power-down Mode, the HF
oscillator is stopped. The 32 kHz oscillator may stay running. The
content of the on-chip RAM and the Special Function Registers are
preserved. Note that the Power-down Mode can not be entered
when the watchdog has been enabled.
The Power-down Mode can be terminated by an external RESET in
the same way as in the 80C51 (RAM is saved, but SFRs are cleared
due to RESET) or in addition by any one of the external interrupts
(INT0, INT1) or Seconds interrupt.
The status of the external pins during Power-down Mode is shown in
Table 40. If the Power-down Mode is activated while in external
program memory, the port data that is held in the Special Function
Register P2 is restored to Port 2.
If the data is a logic1, the port pin is held HIGH during the
Power-down Mode by the strong pull-up transistor P1 (see Figure 9).
The Power-down Mode should not be entered within an interrupt
routine because Wake-up with an external or ‘Seconds’ interrupt is
not possible in that case.
6.11.4
Wake-up from Power-down Mode
The Power-down Mode of the P8xC557E4 can also be terminated
by any one of the three enabled interrupts, INT0, INT1 or Seconds
interrupt.
If there is an interrupt already in service, which has same or higher
priority as the Wake-up interrupt, Power-down Mode will switch over
to Idle Mode and stay there until an interrupt of higher priority
terminates Idle Mode.
A termination with these interrupts does not affect the internal data
memory and does not affect the Special Function Registers. This
gives the possibility to exit Power-down without changing the port
output levels. To terminate the Power-down Mode with an external
interrupt, INT0 or INT1 must be switched to be level-sensitive and
must be enabled. The external interrupt input signal INT0 or INT1
must be kept LOW till the oscillator has restarted and stabilized (see
Figure 41). A Seconds interrupt will terminate the Power-down Mode
if it is enabled and INT1 is level sensitive. In order to prevent any
interrupt priority problems during Wake-up, the priority of the desired
Wake-up interrupt should be higher than the priorities of all other
enabled interrupt sources.
The instruction following the one that put the device into the
Power-down Mode will be the first one which will be executed after
the interrupt routine has been serviced.
6.12
Oscillator Circuits
The input signal SELXTAL1 connected to logic “1” selects the
XTAL1, 2 oscillator (standard 80C51) instead of the XTAL3, 4
oscillator, which is halted and XTAL3, 4 must not be connected.
6.12.1
XTAL1, 2 Oscillator circuit (standard 80C51)
The oscillator circuit of the P8xC557E4 is a single-stage inverting
amplifier in a Pierce oscillator configuration. The circuitry between
the XTAL1 and XTAL2 is basically an inverter biased to the transfer
point. Either a crystal or ceramic resonator can be used as the
feedback element to complete the oscillator circuitry. Both are
operated in parallel resonance. XTAL1 is the high gain amplifier
input, and XTAL2 is the output (see Figure 42). To drive the
P8xC557E4 externally, XTAL1 is driven from an external source and
XTAL2 left open-circuit (see Figure 43).
6.12.2
XTAL3, 4 Circuitry
Please refer to chapter 6.13.1
Figure 42. Using the On-Chip Oscillator.
Quartz crystal
or ceramic
resonator
C1
C2
XTAL1
XTAL2
VSS
C1 = C2 = 20pF
External
clock
signal
XTAL2
XTAL1
VSS
Figure 43. Using an external clock.
SELXTAL1
1
SELXTAL1
1
(NC)
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