- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄36334 > 935262922557 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935262922557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 91/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935262922557 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)當(dāng)前第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
1998 Apr 09
48
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
114
RPS_RE0
26
R
RPS Task 0 Register access Error: this bit is set when the LDREG,
STREG or MASKWRITE command tries to access a non-existing
register. This bit is reset by writing a logic 1 to the RPS_E0 bit in the ISR
or when a new RPS Task 0 is started.
RPS_PE0
25
R
RPS Task 0 Page Error: this bit is set when the RPS Task 0 tries to
write-access an address outside the 4-kbyte page. This bit is reset by
writing a logic 1 to the RPS_E0 bit in the ISR or when a new RPS Task 0
is started.
RPS_A0
24
R
RPS Task 0 Active: this bit is set whenever RPS Task 0 is executing
and not staying in a wait condition or uploading the working registers
DEBI_TO
23
R
DEBI Time Out: this bit is set when the TIMEOUT value was reached.
This bit is reset by writing a logic 1 to the DEBI_E bit in the ISR. Reset
value is a logic 1.
DEBI_EF
22
R
DEBI Format Error: this bit indicates an illegal command to immediate
transfer across a Dword boundary. This bit is reset by writing a logic 1 to
the DEBI_E bit in the ISR.
IIC_EA
21
R
I2C-bus Address Error: this bit is set when there is no acknowledge
after the device address. This bit is reset by writing a logic 1 to the IIC_E
bit in the ISR or when a new I2C-bus command starts.
IIC_EW
20
R
I2C-bus Write data Error: this bit is set when there is no acknowledge
during the writing of the data byte(s). This bit is reset by writing a logic 1
to the IIC_E bit in the ISR or when a new I2C-bus command starts.
IIC_ER
19
R
I2C-bus Read data Error This bit is set when there is no acknowledge
during reading of the data byte(s). This bit is reset by writing a logic 1 to
the IIC_E bit in the ISR or when a new I2C-bus command starts.
IIC_EL
18
R
I2C-bus Loss arbitration Error: this bit is set when the I2C-bus loses its
arbitration. This bit is reset by writing a logic 1 to the IIC_E bit in the ISR
or when a new I2C-bus command starts.
IIC_EF
17
R
I2C-bus Frame Error: this bit is set when there is an invalid
START/STOP condition since the last I2C-bus command. This bit is
reset by writing a logic 1 to the IIC_E bit in the ISR or when a new
I2C-bus command starts.
V3P
16
R
Video DMA 3 Protection error: this bit is set when video DMA3
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
V2P
15
R
Video DMA 2 Protection error: this bit is set when video DMA2
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
V1P
14
R
Video DMA 1 Protection error: this bit is set when video DMA1
generates an address during an active transmission beyond its
protection address. This bit is reset by writing a logic 1 to the V_PE bit in
the ISR or by reloading the DMA base address.
VF3
13
R
Video FIFO 3 underow/overow: this bit is set when the video FIFO 3
has an overow/underow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935242220551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935242220557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935260698551 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935260698557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935260699551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。