參數(shù)資料
型號： 935262451557
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100
文件頁數(shù)： 123/144頁
文件大小： 592K
代理商： 935262451557
2000 Mar 15
8
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
RTCO
36
(I/)O
real-time control output; contains information about actual system clock
frequency, eld rate, odd/even sequence, decoder status, subcarrier frequency
and phase and PAL sequence (see external document
“RTC Functional
Description”, available on request); the RTCO pin is enabled via I2C-bus
bit RTCE; see notes 2, 3 and Table 34
AMCLK
37
O
audio master clock output, up to 50% of crystal clock
VSSD(ICO1)
38
P
internal digital core supply ground 1
ASCLK
39
O
audio serial clock output
ALRCLK
40
(I/)O
audio left/right clock output; can be strapped to supply via a 3.3 k
resistor to
indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)
has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4
AMXCLK
41
I
audio master external clock input
ITRDY
42
I
target ready input, image port (with internal pull-up)
VDDD(ICO2)
43
P
internal digital core supply voltage 2 (+3.3 V)
TEST0
44
O
do not connect; reserved for future extensions and for testing: scan output
ICLK
45
I/O
clock output signal for image port, or optional asynchronous back-end clock
input
IDQ
46
O
output data qualier for image port (optional: gated clock output)
ITRI
47
I(/O)
image port output control signal, effects all input port pins inclusive ICLK, enable
and active polarity is under software control (bits IPE in subaddress 87H); output
path used for testing: scan output
IGP0
48
O
general purpose output signal 0; image port (controlled by subaddresses
84H and 85H)
IGP1
49
O
general purpose output signal 1; image port (controlled by subaddresses
84H and 85H)
VSSD(EP2)
50
P
external digital pad supply ground 2
VDDD(EP3)
51
P
external digital pad supply voltage 3 (+3.3 V)
IGPV
52
O
multi purpose vertical reference output signal; image port (controlled by
subaddresses 84H and 85H)
IGPH
53
O
multi purpose horizontal reference output signal; image port (controlled by
subaddresses 84H and 85H)
IPD7 to IPD4
54 to 57
O
image port data outputs
VDDD(ICO3)
58
P
internal digital core supply voltage 3 (+3.3 V)
IPD3 to IPD0
59 to 62
O
image port data output
VSSD(ICO2)
63
P
internal digital core supply ground 2
HPD7 to HPD4
64 to 67
I/O
host port data I/O, carries UV chrominance information in 16-bit video I/O modes
VDDD(ICO4)
68
P
internal digital core supply voltage 4 (+3.3 V)
HPD3 to HPD0
69 to 72
I/O
host port data I/O, carries UV chrominance information in 16-bit video I/O modes
TEST1
73
I
do not connect; reserved for future extensions and for testing: scan input
TEST2
74
I
do not connect; reserved for future extensions and for testing: scan input
VDDD(EP4)
75
P
external digital pad supply voltage 4 (+3.3 V)
VSSD(EP3)
76
P
external digital pad supply ground 3
TEST3
77
I
do not connect; reserved for future extensions and for testing: scan input
SYMBOL
PIN
TYPE
DESCRIPTION
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