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參數(shù)資料
| 型號(hào)： | 935249730118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-109, SO-16 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 42K |
| 代理商： | 935249730118 |
January 1995
4
Philips Semiconductors
Product specication
12-stage binary counter
HEF4040B
MSI
Note
1. For other loads than 50 pF at the nth output, use the slope given.
Minimum clock
5
50
25
ns
see also waveforms
Fig.4
pulse width; HIGH
10
tWCPH
30
15
ns
15
20
10
ns
Minimum MR
5
40
20
ns
pulse width; HIGH
10
tWMRH
30
15
ns
15
20
10
ns
Recovery time
5
40
20
ns
for MR
10
tRMR
30
15
ns
15
20
10
ns
Maximum clock
5
10
20
MHz
pulse frequency
10
fmax
15
30
MHz
15
25
50
MHz
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
400 fi +∑ (foCL) × VDD2
where
dissipation per
10
2 000 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
5 200 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
VDD
V
SYMBOL
MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
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