參數(shù)資料
型號: 935242210551
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, SOT-322, QFP-160
文件頁數(shù): 9/147頁
文件大?。?/td> 526K
代理商: 935242210551
1998 Apr 09
106
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 93 Timing parameters (tPCI: PCI clock cycle time, minimum 30 ns)
Note
1. Only relevant to stretch access cycles in Intel mode. tmin can be negative, i.e. RDY can be set to LOW before falling
edge of RDN/WRN.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
tas
address set-up time
tPCI 15
ns
tah
address hold time
tPCI 10
ns
talh
delay between de-asserting of RDN/WRN
and ALE
tPCI 15
ns
taz
address 3-state time before start of read
command
tPCI 10
ns
tdhw
write data output hold time
3
ns
tdhr
read data input hold time
0
ns
tdsw
write data output set-up time
tPCI 15
ns
tdsrh
read data input set-up time (relative to
handshake edge)
0.7tPCI
ns
tdsrd
read data input set-up time (dumb target,
no handshake)
20
ns
tidl
idle time before new transfer starts with
AS_ALE (increment mode)
write access
2tPCI 10
ns
read access
3tPCI 10
ns
trwi
idle time between two data access strobes
in non-increment mode; this parameter
depends on FAST mode enable
fast mode
tPCI 10
ns
normal mode
2tPCI 10
ns
trdy
RDY assertion time (Intel mode)
1.5tPCI
ns
tmin
delay from negative edge of RDN/WRN to
de-assertion of RDY; TIMEOUT should be
adjusted to TIMEOUT = tmin +1
note 1
(TIMEOUT
0.5)tPCI ns
tdz
time until slave driven data lines have to
go to 3-state, after read cycle is nished
2.0 tPCI
ns
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