1998 Apr 09
110
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.15.4.4
Command word description
To configure and initiate a transfer there are 3 PCI memory mapped command words. A DEBI register upload after
writing to DEBI_COMMAND starts the transfer process.
Table 95 DEBI_CONFIG
Table 96 DEBI_COMMAND
Table 97 DEBI_PAGE
Table 98 DEBI_AD
OFFSET
NAME
BIT
TYPE
DESCRIPTION
7CH
XIRQ_EN
31
RW
enable external interrupt on GPIO3
XRESUME
30
RW
resume block transfer when XIRQ was de-asserted
29
reserved
FAST
28
RW
enable fast mode (short trwi time)
27 and 26
reserved
TIMEOUT [3:0]
25 to 22
RW
timer set-up value (PCI clock cycles)
SWAP
21 and 20
RW
endian swap type:
00: straight - don’t swap
01: 2-byte swap
10: 4-byte swap
11: reserved
SLAVE16
19
RW
indicates that slave is able to serve 16-bit cycles
INCREMENT
18
RW
enables address increment for block transfer
INTEL
17
RW
Intel style bus handshake if HIGH, else Motorola style
TIEN
16
RW
timer enable (active LOW)
15 to 0
reserved
OFFSET
NAME
BIT
TYPE
DESCRIPTION
80H
BLOCKLENGTH
[14:0]
31 to 17
RW
BLOCKLENGTH > 4: block transfer length in bytes
4
≥ BLOCKLENGTH > 0: immediate transfer 1 to 4 bytes
BLOCKLENGTH = 0: reserved
WRITE_N
16
RW
transfer direction (write if LOW)
A16_IN
15 to 0
RW
slave target start address
OFFSET
NAME
BIT
TYPE
DESCRIPTION
84H
DEBI_PAGE
31 to 12
RW
DEBI page table address (not used if PAGE_EN = 0)
PAGE_EN
11
RW
enable address paging
10 to 0
reserved
OFFSET
NAME
BIT
TYPE
DESCRIPTION
88H
DEBI_AD
31 to 0
RW
data input/output in immediate mode or DMA start address
for block transfer (Dword aligned, DEBI_AD [1:0] have to be
set to logic 0)