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參數(shù)資料
| 型號： | 935187410118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 172K |
| 代理商： | 935187410118 |
Philips Semiconductors - PIP - 74HC/HCT259; 8-bit addressable latch
Product Information
74HC/HCT259; 8-bit
addressable latch
Information as of 2003-04-22
Stay informed
Download datasheet
Applications
Block diagram
topGeneral description
The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in
digital systems. The '259' are multifunctional devices capable of storing single-line data in eight addressable latches,
and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available.
The '259' also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The '259' has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the
data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed
latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are
unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other
outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data
(D) input. When operating the '259' as an addressable latch, changing more than one bit of address could impose a
transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table
summarizes the operations of the '259'.
topFeatures
q
Combines demultiplexer and 8-bit latch
q
Serial-to-parallel capability
q
Output from each storage bit available
q
Random (addressable) data entry
q
Easily expandable
q
Common reset input
q
Useful as a 3-to-8 active HIGH decoder
q
Output capability: standard
q
ICC category: MSI
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