參數(shù)資料
型號： 935187410118
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16
封裝： SOT-338-1, SSOP-16
文件頁數(shù)： 3/15頁
文件大?。?/td> 172K
代理商： 935187410118
December 1990
11
Philips Semiconductors
Product specication
8-bit addressable latch
74HC/HCT259
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
相關PDF資料
PDF描述
935187400112 HCT SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16
935188440118 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
935188440112 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
933713990652 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
935188430118 HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
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