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參數(shù)資料
| 型號： | 935044170112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38, DIP-16 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 240K |
| 代理商： | 935044170112 |
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1999 Jan 11
33
Philips Semiconductors
Product specication
PLL with bandgap controlled VCO
74HCT9046A
PLL design example
The frequency synthesizer used in
the design example shown in Fig.34
has the following parameters:
Output frequency: 2 MHz to 3 MHz.
Frequency steps: 100 kHz.
Settling time: 1 ms.
Overshoot: <20%.
The open loop gain is:
H (s)
× G (s) = Kp × Kf × Ko × Kn
and the closed loop:
where:
Kp = phase comparator gain
Kf = low-pass filter transfer gain
Ko = Kv/s VCO gain
Kn = 1n divider ratio.
The programmable counter ratio Kn
can be found as follows:
The VCO is set by the values of R1,
R2 and C1; R2 = 10 k
(adjustable).
The values can be determined using
the information in Table 3.
With fc = 2.5 MHz and fL = 500 kHz
this gives the following values
(VCC = 5.0 V):
R1 = 30 k
.
R2 = 30 k
.
C1 = 100 pF.
The VCO gain is:
Φ
u
Φ
i
-------
K
p
K
f
×
K
o
×
K
n
×
1K
p
K
f
K
o
×
K
n
×
+
------------------------------------------------------
=
N
min
f
OUT
f
step
------------
2MHz
100 kHz
----------------------
20
==
=
N
max
f
OUT
f
step
------------
3MHz
100 kHz
----------------------
30
==
=
K
v
2f
L
2
π
×
V
CC
1.1
–
() 1.1
–
----------------------------------------------
1MHz
2.8
-----------------
2
π
×
2.24
10
6
×
rs
V
≈
==
The gain of the phase comparator
PC2 is:
Using PC2 with the passive filter as
shown in Fig.34 results in a high gain
loop with the same performance as a
loop with an active filter. Hence loop
filter equations as for a high gain loop
should be used. The current source
output of PC2 can be simulated then
with a fictive filter resistance:
The transfer functions of the filter is
given by:
Where:
τ1 = R3' × C2.
τ2 = R4 × C2.
The characteristic equation is:
This results in:
or:
This can be written as:
with the natural frequency
ω
n defined
as:
and the
damping value given as:
In Fig.35 the output frequency
response to a step of input frequency
is shown.
The overshoot and settling time
percentages are now used to
determine
ω
n. From Fig.35 it can be
K
p
5
4
π
×
------------
0.4V r
==
R3'
R
b
17
-------
=
K
f
1s
τ
2
+
s
τ
2
------------------
=
1K
p
K
f
×
K
o
×
K
n
×
+
1K
p
1s
τ
2
+
s
τ
1
------------------
K
v
s
------ K
n
0
=
+
s
2
sK
p Kv Kn
τ
2
τ
1
-----
K
p Kv Kn τ1
0
=
++
s
2
ζω
n s
ω
n
()
2
+
0
=
ω
n
K
p
K
v
K
n
×
τ
1
--------------------------------
=
ζ
0.5
τ
2
ω
n
×
=
seen that the damping ratio
ζ = 0.707
will produce an overshoot of less than
20% and settle to within 5% at
ω
nt = 5.
The required settling time is 1 ms.
This results in:
Rewriting the equation for natural
frequency results in:
The maximum overshoot occurs at
Nmax = 30; hence Kn = 130:
When C2 = 470 nF, it follows:
Hence the current source bias
resistance Rb = 17 × 2550 = 43 k.
With
ζ = 0.707 (0.5 × τ2 × ωn) it
follows:
For extra ripple suppression a
capacitor C3 can be connected in
parallel with R4, with an extra
τ
3 =R4 × C3.
For stability reasons
τ3 should be
<0.1τ2, hence C3 < 0.1C2, or
C3 = 39 nF.
ω
n
5
t
---
5
0.001
---------------
510
3
×
rs
==
=
τ
1
K
p
K
v
×
K
n
×
ω
n
()
2
--------------------------------
=
τ
1
0.4
2.24
×
10
6
×
5000
2
30
×
------------------------------------------
0.0012
==
R3'
τ
1
C2
--------
0.0012
470
10
9
–
×
----------------------------
2550
==
=
τ
2
0.707
0.5
5000
×
----------------------------
0.00028
==
R4
τ
2
C2
--------
0.00028
470
10
9
–
×
----------------------------
600
==
=
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