參數(shù)資料
型號: 935044170112
廠商: NXP SEMICONDUCTORS
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, PDIP16
封裝: 0.300 INCH, PLASTIC, SOT-38, DIP-16
文件頁數(shù): 18/40頁
文件大?。?/td> 240K
代理商: 935044170112
1999 Jan 11
25
Philips Semiconductors
Product specication
PLL with bandgap controlled VCO
74HCT9046A
Fig.28 Typical power dissipation.
10 3
MBD109
102
10
10 4
P DEM
(W)
R (k
)
s
V
=
CC
5.5 V
4.5 V
10 5
10 3
APPLICATION INFORMATION
This information is a guide for the approximation of values
of external components to be used with the 74HCT9046A
in a phase-locked-loop system.
Values of the selected components should be within the
rages shown in Table 2.
Table 2 Survey of components.
COMPONENT
VALUE
R1
between 3 k
and 300 k
R2
between 3 k
and 300 k
R1 + R2
parallel value >2.7 k
C1
>40 pF
Table 3 Design considerations for VCO section.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATION
VCO frequency without
extra offset
PC1, PC2
VCO frequency characteristic
With R2 =
∞ and R1 within the range 3 k< R1 < 300 k, the
characteristics of the VCO operation will be as shown in Fig.29a.
(Due to R1, C1 time constant a small offset remains when R2 =
∞).
PC1
Selection of R1 and C1
Given fc, determine the values of R1 and C1 using Fig.31.
PC2
Given fmax and fc determine the values of R1 and C1 using Fig.31; use
Fig.33 to obtain 2fL and then use this to calculate fmin.
VCO frequency
with extra offset
PC1, PC2
VCO frequency characteristic
With R1 and R2 within the ranges 3 k
< R1 < 300 k< R2 < 300 k,
the characteristics of the VCO operation is as shown in Fig.29b.
PC1, PC2
Selection of R1, R2 and C1
Given fc and fL determine the value of product R1C1 by using Fig.33.
Calculate foff from the equation foff = fc 1.6fL.
Obtain the values of C1 and R2 by using Fig.32.
Calculate the value of R1 from the value of C1 and the product R1C1.
PLL conditions with no
signal at the SIGIN input
PC1
VCO adjusts to fc with ΦPCIN = 90° and VVCOIN = 12VCC.
PC2
VCO adjusts to foffset with ΦPCIN = 360° and VVCOIN = minimum.
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