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參數(shù)資料
| 型號： | 933876880602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | F/FAST SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 933876880602 |
Philips Semiconductors
Product specification
74F393
Dual 4-bit binary ripple counter
2
1988 Nov 01
853–0295 94977
FEATURES
Two 4-bit binary counters
Two Master Resets to clear each 4-bit counter individually
DESCRIPTION
The 74F393 is a Dual Ripple Counter with separate Clock (CPn) and
Master Reset (MR) inputs to each counter. The two counters are
identified by the “a” and “b” suffixes in the pin configuration. The
operation of each half of the 74F393 is the same. The counters are
triggered by a High-to-Low transition of the Clock (CPa and CPb)
inputs. The counter outputs are internally connected to provide
Clock inputs to succeeding stages. The outputs of the ripple counter
do not change synchronously and should not be used for high speed
address decoding. The Master Resets (MRa and MRb) are active
High asynchronous inputs; one for each 4-bit counter. A High level
in the MR input overrides the Clock and sets the outputs Low.
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
Q1b
Q2b
Q3b
Q0b
CPb
MRb
CPa
MRa
Q3a
Q0a
Q1a
Q2a
SF00704
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F393
125MHz
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
14-pin plastic DIP
N74F393N
SOT27-1
14-pin plastic SO
N74F393D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
CPa, CPb
Clock inputs
1.0/1.0
20
A/0.6mA
MRa, MRb
Master Reset inputs
1.0/1.0
20
A/0.6mA
Qna – Qnb
Data outputs
50/33.3
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
13
1
CPa
CPb
34
5
6
11
10
9
8
Q0a
Q1a
Q2a
Q3a
Q0b Q1b Q2b
Q3b
12
2
MRa
MRb
SF00705
VCC = Pin 14
GND = Pin 7
IEC/IEEE SYMBOL (IEEE/IEC)
SF00706
CTR DIV 16
2
1
12
13
3
4
5
6
11
10
9
8
CT=0
+
0
3
0
3
CTR DIV 16
CT=0
+
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