參數(shù)資料
型號(hào)： 933768140118
廠商： NXP SEMICONDUCTORS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO16
封裝： 7.50 MM, PLASTIC, MS-013, SOT-162-1, SO-16
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 139K
代理商： 933768140118
2003 Jan 27
5
Philips Semiconductors
Product specication
8-bit A/D and D/A converter
PCF8591
7
FUNCTIONAL DESCRIPTION
7.1
Addressing
Each PCF8591 device in an I2C-bus system is activated by
sending a valid address to the device. The address
consists of a fixed part and a programmable part. The
programmable part must be set according to the address
pins A0, A1 and A2. The address always has to be sent as
the first byte after the start condition in the I2C-bus
protocol. The last bit of the address byte is the
read/write-bit which sets the direction of the following data
transfer (see Figs 4, 16 and 17).
7.2
Control byte
The second byte sent to a PCF8591 device will be stored
in its control register and is required to control the device
function. The upper nibble of the control register is used for
enabling the analog output, and for programming the
analog inputs as single-ended or differential inputs. The
lower nibble selects one of the analog input channels
defined by the upper nibble (see Fig.5). If the
auto-increment flag is set, the channel number is
incremented automatically after each A/D conversion.
If the auto-increment mode is desired in applications
where the internal oscillator is used, the analog output
enable flag in the control byte (bit 6) should be set. This
allows the internal oscillator to run continuously, thereby
preventing conversion errors resulting from oscillator
start-up delay. The analog output enable flag may be reset
at other times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the
highest available channel number being allocated.
Therefore, if the auto-increment flag is set, the next
selected channel will be always channel 0. The most
significant bits of both nibbles are reserved for future
functions and have to be set to logic 0. After a Power-on
reset condition all bits of the control register are reset to
logic 0. The D/A converter and the oscillator are disabled
for power saving. The analog output is switched to a
high-impedance state.
handbook, halfpage
MBL823
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
VSS
VDD
AOUT
VREF
AGND
EXT
OSC
SCL
SDA
PCF8591T
Fig.3 Pinning diagram (SO16).
handbook, halfpage
MBL824
1
msb
lsb
0
fixed part
programmable part
1
A2
A1
A0
R/W
Fig.4 Address byte.
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