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參數(shù)資料
| 型號(hào)： | 933669680652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 933669680652 |
December 1990
2
Philips Semiconductors
Product specication
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q0 to Q9),
an active LOW output from the most significant flip-flop
(Q5-9), active HIGH and active LOW clock inputs (CP0 and
CP1) and an overriding asynchronous master reset input
(MR).
The counter is advanced by either a LOW-to-HIGH
transition at CP0 while CP1 is LOW or a HIGH-to-LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, the Q5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero
(Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the
clock inputs (CP0 and CP1).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi+∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP0, CP1 to Qn
CL = 15 pF; VCC = 5 V 2021ns
fmax
maximum clock frequency
77
67
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
35
36
pF
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