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參數資料
| 型號： | 933669680652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 12/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 933669680652 |
December 1990
9
Philips Semiconductors
Product specication
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to+85
40 to+125
min.
typ.
max
.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP0 to Qn
25
46
58
69
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
CP0 to Q5-9
25
46
58
69
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
CP1 to Qn
25
50
63
75
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
CP1 to Q5-9
25
50
63
75
ns
4.5
Fig.9
tPHL
propagation delay
MR to Q19
22
46
58
69
ns
4.5
Fig.8
tPLH
propagation delay
MR to Q59, Q0
20
46
58
69
ns
4.5
Fig.8
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.9
tW
clock pulse width
HIGH or LOW
16
7
20
24
ns
4.5
Fig.8
tW
master reset pulse
width; HIGH
16
4
20
24
ns
4.5
Fig.8
trem
removal time
MR to CP0, CP1
5
ns
4.5
Fig.8
tsu
set-up time
CP1 to CP0;
CP0 to CP1
10
3
13
15
ns
4.5
Fig.7
th
hold time
CP0 to CP1;
CP1 to CP0
10
6
13
15
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
30
61
24
20
ns
4.5
Fig.8
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