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參數(shù)資料
| 型號(hào)： | 9334DMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Addressable Latch |
| 中文描述： | 93 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | 9334DMQB |
Switching Characteristics
at V
CC
e
5V and T
A
e
25
§
C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
R
L
e
400
X
, C
L
e
15 pF
Units
Min
Max
t
PLH
Propagation Delay Time
Low to High Level Output
Enable to
Output, Fig. 1
28
ns
t
PHL
Propagation Delay Time
High to Low Level Output
Enable to
Output, Fig. 1
27
ns
t
PLH
Propagation Delay Time
Low to High Level Output
Data to
Output, Fig. 2
35
ns
t
PHL
Propagation Delay Time
High to Low Level Output
Data to
Output, Fig. 2
28
ns
t
PLH
Propagation Delay Time
Low to High Level Output
Address to
Output, Fig. 3
35
ns
t
PHL
Propagation Delay Time
High to Low Level Output
Address to
Output, Fig. 3
35
ns
t
PHL
Propagation Delay Time
High to Low Level Output
Clear to
Output, Fig. 5
31
ns
Function Tables
E
C
Mode
L
H
L
H
H
L
Addressable Latch
Memory
Active High Eight
Channel Demultiplexer
Clear
H
L
Inputs
Present Output States
Mode
C
E
D
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
X
X
X
X
L
L
L
L
L
L
L
L
Clear
L
L
L
L
#
#
#
L
L
L
L
L
#
#
#
L
L
H
L
H
#
#
#
H
L
L
H
H
L
L
L
L
#
#
#
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
#
#
#
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Demultiplex
H
H
L
L
L
L
L
L
H
H
H
X
X
X
X
Q
N
b
1
Memory
H
H
H
H
#
#
#
H
H
L
L
L
L
#
#
#
L
L
L
H
L
H
#
#
#
L
H
L
L
H
H
L
L
L
L
#
#
#
H
H
L
L
L
L
L
H
Q
N
b
1
Q
N
b
1
L
H
Q
N
b
1
Q
N
b
1
Q
N
b
1
Q
N
b
1
#
#
#
Q
N
b
1
Q
N
b
1
Q
N
b
1
Addressable
Latch
H
H
H
H
Q
N
b
1
Q
N
b
1
Q
N
b
1
Q
N
b
1
L
H
X
e
Don’t Care Condition
L
e
Low Voltage Level
H
e
High Voltage Level
Q
N
b
1
e
Previous Output State
3
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