參數(shù)資料
型號(hào)： 933372700653
廠商： NXP SEMICONDUCTORS
元件分類： 計(jì)數(shù)器
英文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁(yè)數(shù)： 5/8頁(yè)
文件大?。?/td> 96K
代理商： 933372700653
January 1995
5
Philips Semiconductors
Product specication
5-stage Johnson counter
HEF4017B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
Output transition
times
5
60
120
ns
10 ns
+ (1,0 ns/pF) C
L
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Hold times
5
90
45
ns
CP0 →CP1
10
thold
40
20
ns
15
20
10
ns
580
40
ns
CP1 → CP0
10
thold
40
20
ns
15
30
10
ns
Minimum clock
pulse width:
5
tWCPL =
tWCPH
80
40
ns
CP0 = LOW;
10
40
20
ns
see also waveforms
CP1 = HIGH
15
30
15
ns
Figs 4 and 5
Minimum MR
5
50
25
ns
pulse width; HIGH
10
tWMRH
30
15
ns
15
20
10
ns
Recovery time
5
60
30
ns
for MR
10
tRMR
30
15
ns
15
20
10
ns
Maximum clock
5
6
12
MHz
pulse frequency
10
fmax
12
24
MHz
15
30
MHz
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
500 fi +∑ (foCL) × VDD2
where
dissipation per
10
2200 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
6000 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
相關(guān)PDF資料
PDF描述
0552-1-57-80-11-84-10-0 BERYLLIUM COPPER, MATTE TIN (200) OVER NICKEL FINISH, PCB TERMINAL
933282490652 SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16
933373490652 SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
933379050005 SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC
933373490653 SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
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