參數(shù)資料
型號： 933372700653
廠商： NXP SEMICONDUCTORS
元件分類： 計數(shù)器
英文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁數(shù)： 4/8頁
文件大?。?/td> 96K
代理商： 933372700653
January 1995
4
Philips Semiconductors
Product specication
5-stage Johnson counter
HEF4017B
MSI
FUNCTION TABLE
MR
CP0
CP1
OPERATION
HX
X
O0 = O5-9 = H; O1 to O9 =L
L
H
Counter advances
L
Counter advances
L
X
No change
L
X
H
No change
L
H
No change
L
No change
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4.
= positive-going transition
5.
= negative-going transition
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0, CP1 → O0 to O9
5
140
280
ns
113 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
55
110
ns
44 ns
+ (0,23 ns/pF) CL
15
40
80
ns
32 ns
+ (0,16 ns/pF) CL
5
125
250
ns
98 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
50
100
ns
39 ns
+ (0,23 ns/pF) CL
15
40
80
ns
32 ns
+ (0,16 ns/pF) CL
CP0, CP1 → O5-9
5
145
290
ns
118 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
55
110
ns
44 ns
+ (0,23 ns/pF) CL
15
40
80
ns
32 ns
+ (0,16 ns/pF) CL
5
125
250
ns
98 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
50
100
ns
39 ns
+ (0,23 ns/pF) CL
15
40
80
ns
32 ns
+ (0,16 ns/pF) CL
MR
→ O1 to O9
5
115
230
ns
88 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
50
100
ns
39 ns
+ (0,23 ns/pF) CL
15
35
70
ns
27 ns
+ (0,16 ns/pF) CL
MR
→ O5-9
5
110
220
ns
83 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
45
90
ns
34 ns
+ (0,23 ns/pF) CL
15
35
70
ns
27 ns
+ (0,16 ns/pF) CL
MR
→ O0
5
130
260
ns
103 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
55
105
ns
44 ns
+ (0,23 ns/pF) CL
15
40
75
ns
32 ns
+ (0,16 ns/pF) CL
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