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參數(shù)資料
| 型號(hào)： | 933277660652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | 933277660652 |
January 1995
4
Philips Semiconductors
Product specication
Dual BCD counter
HEF4518B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0 , CP1 → On
5
120
240 ns
93 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
55
110 ns
44 ns
+ (0,23 ns/pF) CL
15
40
80 ns
32 ns
+ (0,16 ns/pF) CL
5
120
240 ns
93 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
55
110 ns
44 ns
+ (0,23 ns/pF) CL
15
40
80 ns
32 ns
+ (0,16 ns/pF) CL
MR
→ On
5
75
150 ns
48 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
35
70 ns
24 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
Output transition
times
5
60
120 ns
10 ns
+ (1,0 ns/pF) C
L
HIGH to LOW
10
tTHL
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
Minimum CP0
560
30
ns
pulse width; LOW
10
tWCPL
30
15
ns
15
20
10
ns
Minimum CP1
560
30
ns
pulse width; HIGH
10
tWCPH
30
15
ns
15
20
10
ns
Minimum MR
5
30
15
ns
pulse width; HIGH
10
tWMRH
20
10
ns
15
16
8
ns
Recovery time
5
50
25
ns
see also waveforms
Figs 4 and 5
for MR
10
tRMR
30
15
ns
15
20
10
ns
Set-up times
5
50
25
ns
CP0 → CP1
10
tsu
30
15
ns
15
20
10
ns
550
25
ns
CP1 → CP0
10
tsu
30
15
ns
15
20
10
ns
Maximum clock
5
8
16
MHz
pulse frequency
10
fmax
15
30
MHz
15
20
40
MHz
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