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參數資料
| 型號： | 933277660652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁數： | 2/7頁 |
| 文件大小： | 64K |
| 代理商： | 933277660652 |
January 1995
2
Philips Semiconductors
Product specication
Dual BCD counter
HEF4518B
MSI
DESCRIPTION
T he HEF4518B is a dual 4-bit internally synchronous BCD
counter. The counter has an active HIGH clock input
(CP0) and an active LOW clock input (CP1), buffered
outputs from all four bit positions (O0 to O3) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP0 input if CP1 is HIGH or the HIGH to
LOW transition of the CP1 input if CP0 is LOW. Either CP0
or CP1 may be used as the clock input to the counter and
the other clock input may be used as a clock enable input.
A HIGH on MR resets the counter (O0 to O3 = LOW)
independent of CP0, CP1.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4518BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4518BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4518BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
CP0A,CP0B
clock inputs (L to H triggered)
CP1A, CP1B
clock inputs (H to L triggered)
MRA,MRB
master reset inputs
O0A to O3A
outputs
O0B to O3B
outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4518B are:
Multistage synchronous counting.
Multistage asynchronous counting.
Frequency dividers.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
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