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參數(shù)資料
| 型號： | 930400801 |
| 廠商： | ATMEL CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP160 |
| 封裝： | MQFPF-160 |
| 文件頁數(shù)： | 43/43頁 |
| 文件大?。?/td> | 673K |
| 代理商： | 930400801 |
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9
AT40KEL040
4155H–AERO–02/06
The Cell
Figure 5 depicts the AT40KEL040 cell. Configuration bits for separate muxes and pass
gates are independent. All permutations of programmable muxes and pass gates are
legal. V
n (V1 -V5) is connected to the vertical local bus in plane n. Hn (H1 -H5) is con-
nected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by
turning on the two pass gates connected to V
n and Hn. Pass gates are opened to let sig-
nals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming
into the logic cell on one local bus plane can be switched onto another plane by opening
two of the pass gates. This allows bus signals to switch planes to achieve greater
routability. Up to five simultaneous local/local turns are possible.
The AT40KEL040 FPGA core cell is a highly configurable logic block based around two
3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This
means that any core cell can implement two functions of 3 inputs or one function of 4
inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated
and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every
cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an impor-
tant feature in the implementation of efficient array multipliers.
Figure 5. The Cell
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40KEL040 architecture well suited to
most digital design application areas (see Figure 6).
OUT
RESET/SET
CLOCK
FB
10
Z
D
Q
"1" NW NE SE SW
"1"
"0"
XW
Y
X
ZW
Y
"1"
N
E
S
W
8X1 LUT
X
Y
NW NE SE SW
N
S
W
V1
H1
V2
H2
V3
H3
V4
H4
V5
H5
"1" OEH OEV
L
Pass gates
X = Diagonal Direct connect or Bus
Y = Orthogonal Direct Connector Bus
W = Bus Connection
Z = Bus Connection
FB = Internal Feed back
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| 930400802 | FPGA, 2304 CLBS, 40000 GATES, PQFP256 |
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| 9308DMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24 |
| 9308FMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP24 |
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