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參數(shù)資料
| 型號： | 930400801 |
| 廠商： | ATMEL CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP160 |
| 封裝： | MQFPF-160 |
| 文件頁數(shù)： | 20/43頁 |
| 文件大?。?/td> | 673K |
| 代理商： | 930400801 |
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27
AT40KEL040
4155H–AERO–02/06
AC Timing
Characteristics
Clocks and Reset Input buffers are measured from a V
IH of 1.5V at the input pad to the internal VIH of 50% of VCC.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
Notes:
1. CMOS buffer delays are measured from a V
IH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
Cell Function
Parameter
Path
Value
Units
Notes
Global Clocks and Set/Reset
GCK Input buffer
t
PD (max)
pad -> clock
3.3
ns
rising edge clock
FCK Input buffer
t
PD (max)
pad -> clock
1.9
ns
rising edge clock
Clock column driver
t
PD (max)
clock -> colclk
1.7
ns
rising edge clock
Clock sector driver
t
PD (max)
colclk -> secclk
0.8
ns
rising edge clock
GSRN Input buffer
t
PD (max)
colclk -> secclk
10.3
ns
Global clock to output
t
PD (max)
clock pad -> out
21.3
ns
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
Fast clock to output
t
PD (max)
clock pad -> out
19.9
ns
rising edge clock
fully loaded clock tree
rising edge DFF
20 mA output buffer
50 pf pin load
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PDF描述 |
|---|---|
| 930400802 | FPGA, 2304 CLBS, 40000 GATES, PQFP256 |
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| 9308DMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24 |
| 9308FMQB | 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP24 |
| 9309-00 | PRESCALER, UUC |
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參數(shù)描述 |
|---|---|
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